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Books/chapters [1]*
J.M.Wang and E.S. Kuh,
“Chebyshev expansion based interconnect
modeling”,
Signal Propagation Journal Papers : J14 A. Mitev, M. Marefat,
D. Ma and J. M. Wang, “Parameter Reduction for Variability Analysis by
SIR Method”, (Invited), IEE Proceedings for Circuits, Devices and
Systems, accepted for publication. J13 D. Ma, J. M. Wang, and M. Song, "Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique", IEEE Transaction on VLSI, accepted for publication. J12 V. Agarwal,
J. Sun and J. M. Wang, “Delay Uncertainty Reduction by
Gate-Interconnect Splitting”, IEEE
Trans. on Circuit and System II, accepted for publication. J11 J. M. Wang, U. Padmanabhan and J. Hu,
“Robust Clock Tree Routing in the Presence of Process
Variations”, IEEE Trans. on
Computer-Aided Design, accepted for publication. J10 J. M. Wang, B. Sukhwani, U. Padmanabhan, D. Ma and K. Singha,
“ Simulation and Design of Nanucircuits with Resonant Tunneling Devices”, IEEE Trans. on Circuits and Systems-I,
Vol. 54, No. 6, pp. 1239-1304, June 2007. J09 K. Muchherla, P. Chen, D. Ma and J. M. Wang, “A
Non-Iterative Equivalent Waveform Model for Timing Analysis in the Presence
of Crosstalk”, ACM Trans. on
Design and Automation of Electronic Systems, accepted for publication. J08 Y. Zhang, J. M. Wang,
L. Xiao, and H. Wu, “Stochastic Modeling for Transmission Lines and
Numerical Experiment Analysis for Transient Simulation”, Journal of
Electronics and Information Technology, Vol. 28, No. 8, pp. 1516 –
1520, August 2006. J07 J. M. Wang, J. Li, S.
Yanamanamanda, K. Vakati,
and K. Muchherla, “Modeling the Driver Load
in the Presence of Process Variations”, IEEE
Trans. on Computer-Aided Design, Vol. 25, No. 10, pp. 2264 - 2275, October 2006. J06 S. Vrudhula, J. M. Wang, and
P. Ghanta, “Hermite
Polynomial Based Interconnect Analysis in the Presence of Process
Variations”, IEEE Trans. on
Computer-Aided Design, Vol. 25, No. 10, pp. 2001-2011, October 2006. J05 Y. Lee, Y. Cao, T. Chen,
J. M. Wang and C. C.-P Chen,
“ HiPRIME: Hierarchical and Passivity
Preserved Interconnect Macromodeling Engine for
RLKC Power Delivery”, IEEE Trans.
on Computer-Aided Design, Vol. 24, No. 6, pp. 797 – 806, June 2005.
J04 J. M. Wang, P. Chen, K.
Muchherla, S. Yanamanamanda
and O. Hafiz, “A Non-Iterative Continuous Model for Switching Window
Computation with Crosstalk Noise”, Invited to The Journal of
Microelectronic Engineering Special Issue on VLSI Design and Test, Elsevier, Vol 3. 2006. J03 L. K. Vakati, K. K. Muchherla,
and J. M. Wang “A New Three-Piece Driver Model with RLC Interconnect
Load”, Transaction of the
Institute of Electronics, Information and Communication Engineers (IEICE),
Vol. E88.A, No. 8, pp. 2206
– 2215, August 2005. J02
J. M. Wang, C. Chu, Q. Yu and E. S. Kuh, “On Projection-based
Algorithms for Model-order Reduction of Interconnects”,
IEEE Trans. on Circuits and Systems I,
Vol. 49, No. 11, pp. 1563 –
1585, November 2002. J01
Q. Yu, J. M. Wang and E. S. Kuh, “Passive
Multipoint Moment Matching Model Order Reduction Algorithm on Multiport Distributed Interconnect Networks”, IEEE Trans. on Circuits and Systems I, Vol. 46, No. 1, pp. 140
– 160, January 1999. Conferences/Symposia: C53 D. Ganesan, A. Mitev, J.
M. Wang, and Y. Cao, “Finite-point gate model
for fast timing and power analysis,” to be published at IEEE International Symposium on Quality
Electronic Design, 2008. C52 S. Varadan,
J. M. Wang, J. Hu , “Handling Partial Correlations in Yield
Prediction”, IEEE Asia
and South Pacific Design Automation Conference (ASPDAC), January 2008 C51 J. Sun, Y. Huang, J.
Li, and Janet M. Wang, “Chebyshev Affine
Arithmetic Based Parametric Yield Prediction Under Limited Descriptions of
Uncertainty”, IEEE Asia and South
Pacific Design Automation Conference (ASPDAC), January 2008 C50
A. Mitev, M. Marefat, D.
Ma and J. M. Wang, “Principle Hessian Direction Based Parameter
Reduction with Process Variation”, nominated as best paper candidate, IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), pp. 632 – 637, November 2007. C49 A. Mitev, D.
Canesan, D. Shammgasundaram,
Y. Cao and J. M. Wang, “ A Robust
Finite-Point Based Gate Model Considering Process Variations”, IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), pp. 692 – 697, November 2007. C48 D. Nguyen, MA. Baysal, E. Toker
and J. M. Wang, “Design and Initial Performance Evaluation of A Full
Field Digital Mammography Upgrade Cassette”, Proceedings of SPIE, September 2007. C47
A. Mitev, M. Marefact, D.
Ma, and J. M. Wang, "Parameter Reduction for Variability Analysis by
Slice Inverse Regression (SIR) Method", IEEE Asia and South Pacific Design Automation Conference (ASPDAC),
pp. 468 – 473, January 2007. C46
V. Agarwal, J. Sun, A. Mitev,
and J. M. Wang, “Delay Uncertainty Reduction by Interconnect and Gate
Splitting”, IEEE Asia and South
Pacific Design Automation Conference (ASPDAC), pp. 690
– 695, January 2007. C45
D. Ma, J. M. Wang, P. Vazquaz "Adaptive On-Chip Power Supply With Robust
One-Cycle Control Technique", IEEE/ACM
International Symposium on Low Power Electronics (ISLPED),
pp. 394 – 399, Germany 2006. C44 U. Padmanabhan,
J. M. Wang and J. Hu, “Statistical Clock Tree
Routing for Robustness to Process Variations”, ACM International Symposium of Physical Design (ISPD), pp. 149 – 156, April 2006. C43
N. Kankani, V. Agarwal
and J. M. Wang, “A Probabilistic Analysis of Pipelined Global
Interconnect Under Process Variations”, IEEE Asia and South Pacific Design Automation Conference (ASPDAC),
pp. 724 – 729, January 2006. C42
V. Agarwal and J. M. Wang, “Yield-Area
Optimizations of Digital Circuits Using Non-dominated Sorting Genetic
Algorithm (YOGA)”, IEEE Asia and
South Pacific Design Automation Conference (ASPDAC), pp.
718 – 723, January 2006. C41 J. M. Wang, B. Srinvas, D. Ma, C. C-P. Chen and J. Li, “System-Level Power and
Thermal Modeling and Analysis by Orthogonal Polynomial based Response Surface
Approach (OPRS)”, IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), pp. 728 – 735, November 2005. C40
R. Jiang,
W. Fu, J. M. Wang, V. Lin and C. C-P. Chen, “Efficient Statistical
Capacitance Variability Modeling
With Orthogonal Principle Factor Analysis”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 683 – 690,
November 2005. C39
D. Ma, J. M. Wang, M. N. Somasundaram and Z. Hu, “Design and Optimization on Dynamic Power
System for Self- Powered Integrated Wireless Sensing Nodes”, International Symposium on Low Power Electronics and
Design (ISLPED), pp. 303 – 306, August 2005. C38
J. M. Wang, A. Mitev and N. Kankani,
“Collocation Method based RC/RLC Extraction with Process
Variation”, Progress in
Electromagnetic Research Symposium (PIERS), abstract, Hangzhou, China, August 2005. C37
Y. Zhang, J. M. Wang, L. Xiao and H. Wu, “Adaptive difference
method and singular treatment approach for fast parameters extraction of
interconnects in MEI system”, Proc. International Conference on Communications, Circuits and
Systems(ICCCS), Vol. 2,
pp. 1196 – 1200, May 2005. C36
B. Sukhwani and J. M. Wang, “A Stepwise
Constant Conductance Approach for Simulating Resonant Tunneling
Diodes”, IEEE International
Symposium on Circuits and Systems (ISCAS),
pp. 2518 – 2521, Kobe, Japan, May 2005. C35
S. Yanamanamanda, J. Li, and J. M. Wang,
“Uncertainty Modeling of Gate Delay Considering Multiple Input
Switching”, IEEE International
Symposium on Circuits and Systems (ISCAS),
pp. 2457 – 2460, Kobe,
Japan, May 2005. C34
K. K. Muchherla, P. Chen and J. M. Wang, “A
Non-Iterative Equivalent Waveform Model For Timing Analysis In Presence of
Crosstalk”, IEEE International
Symposium on Circuits and Systems (ISCAS),
pp. 2465 – 2468, Kobe, Japan, May 2005. C33
C. Talarico, B.S. Pillilli,
K.L Vakati and J.M. Wang, “Early Assessment
of Leakage Power for System Level
Design”, International Symposium
of Quality Design (ISQED), pp. 133 – 136,
March 2005. (Best Paper Award
Candidate) C32
B. Sukhwarni, U. Padmanabhan,
and J. M. Wang, “Nano-Sim: A Step Wise
Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit
Design”, Proc. Design, Automation
and Test in Europe (DATE), pp. 133 – 136, March 2005. C31
P. Ghanta, S. Vrudhula,
R. Panda, and J.M. Wang, “Stochastic Power Grid Analysis Considering
Process Variations”, Proc.
Design, Automation and Test in Europe (DATE), pp. 964 –
969, March 2005. C30
S. Y. Kumar, J. Li, C. Talarico and J. M. Wang,
“A Probabilistic Collocation Method Based Statistical Gate Delay Model
Considering Process Variations and Multiple Input Switching”, Proc. Design, Automation and Test in
Europe (DATE), pp. 770 – 775, March 2005. C29
V. Agarwal, N. Kankani,
R. Rao, S. Bhardwaj, and
J.M. Wang, “An Efficient Combinationality
Check Techniques for the Synthesis of Cyclic Combinational Circuits”, IEEE Asia and South Pacific Design
Automation Conference (ASPDAC), pp. 212 – 215,
January 2005. C28
P. Saxena, L.N. Kumar, G. Hans, and J.M. Wang,
“A Perturbation-aware Noise Convergence Methodology for High
Performance Microprocessors”, IEEE
Asia and South Pacific Design Automation Conference (ASPDAC),
pp. 717 – 722, January 2005. C27
J. M. Wang, P.Ghanta, and S. Vrudhula,
“Stochastic Analysis of Interconnect Networks in the Presence of Process
Variations”, IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), pp. 880
– 887, November 2004. C26
J. M. Wang, O. A. Hafiz and J. Li, “A Linear Fractional Transform (LFT)
Based Model for Interconnect
Parametric Uncertainty ”, Proc. ACM/IEEE Design Automation
Conference (DAC), pp. 375
– 380, June 2004. C25 S. Raj, S. Vrudhula and J. M. Wang, “A Methodology to Improve
Timing Yield in the Presence of Process Variations”, Proc. ACM/IEEE Design Automation
Conference (DAC), pp. 448
– 453, June 2004. C24
J. M. Wang, and O. Hafiz, “Matrix Pencil based Realizable Reduction for
distributed interconnects”, IEEE
International Symposium on Circuits and Systems (ISCAS), pp. 177 – 180, May 2004. C23
L.K.Vakati and J. M. Wang, “A New Three-Ramp
Driver Model with RLC Interconnect Load”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 269 – 272, May
2004. C22
O.Hafiz, J.M.Wang,
“A New Non-iterative model for Switching Window Computation with
Crosstalk Noise”, IEEE
International Symposium on Circuits and Systems (ISCAS), pp. 497 – 500, May 2004. C21
J.M.Wang and O.Hafiz,
“Predicting Interconnect Uncertainty with a New Robust Model Order
Reduction Method”, International
Symposium of Quality Design (ISQED), pp. 363 – 368,
March 2004. C20
J.M.Wang, K.K Muchherla, and J. G. Kumar, “A Clustering
Based Area I/O Planning for Flip-Chip Technology”, International Symposium of Quality Design
(ISQED),
pp. 196 – 201, March 2004. C19
S. Raj, S. Vrudhula and J.M.Wang, “Statistical Gate Sizing to Increase
Timing Yield”, ACM/IEEE
International Workshop on Timing Issues (TAU), February 2004. C18
L.K.Vakati and J. M. Wang, “A New Multi-Ramp
Driver Model With RLC Interconnect Load”, ACM International
Symposium on Physical Design (ISPD), pp. 170 – 175, April 2004. C17
J. M. Wang, O. Hafiz and P. Chen, “A Non-iterative Model for Switching
Window Computation with Crosstalk Noise”, IEEE
Asia and South Pacific Design Automation Conference (ASPDAC),
pp. 847 – 852, January 2004. C16
J.M.Wang, P. Saxena, O.
Hafiz and X. Wang, “Realizable Parasitic Reduction for Distributed
Interconnects Using Matrix Pencil Technique”, IEEE Asia and South Pacific Design Automation Conference (ASPDAC),
pp. 781 – 786, January
2004. C15 J.M. Wang, P. Chen and O. Hafiz,
“Switching Windows Computation in the Presence of Crosstalk Noise”, Proc. International Conference on VLSI,
Las Vegas, pp. 114 – 118, June 2003. C14
J. M. Wang, P. Chen and O. Hafiz, “A New Continuous Switching Window
Computation with Crosstalk Noise”, 16th
Symposium on Integrated Circuits and
Systems Design, pp. 261 – 266, September 2003. C13
Q. Yu, J. M. Wang and E.S. Kuh, “Passive
model order reduction algorithm based on Chebyshev
expansion impulse response of interconnect networks”, Proc. ACM/IEEE Design Automation
Conference (DAC),
pp. 520 – 525, Los Angeles, California, June 2000. C12
J. M. Wang and T. V. Nguyen, “Extended Krylov
Subspace Method for Reduced Order Analysis of Linear Circuits with Multiple
Sources”, Proc. ACM/IEEE Design
Automation Conference (DAC), pp. 247-252, June 2000. C11
J. M. Wang, E. S. Kuh and Q. Yu, “The Chebyshev expansion based reduced order model for
distributed interconnect networks”, IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), pp. 370
– 375, November 1999. C10 J. M. Wang and E.S. Kuh, “Recent Development in Interconnect
Modeling”, European Conference on
Circuit Theory and Design (ECCTD),
pp100-140, 1999. C09
J. M. Wang, Q. Yu and E. S. Kuh, “Coupled
Noise Estimation for distributed RC Interconnect Model”, Proc. Design, Automation and Test in
Europe (DATE), pp. 664 – 668, March 1999. C08 Q. Yu, J.M. Wang and E.S. Kuh, “Multipoint multiport
algorithm for passive reduced-order model of interconnect networks”, IEEE International Symposium on Circuits
and Systems (ISCAS), pp. 74
– 77, June 1998. C07 Q. Yu, J. M. Wang and E. S. Kuh, “Multipoint Moment Matching Model for Multiport Distributed Interconnect Networks”, IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), pp. 85 – 91, November 1998. C06
J. Mao, J. M. Wang and E.S. Kuh, “Simulation
and Sensitivity Analysis of Transmission Line Circuits by the Characteristics
Method”, IEEE/ACM International
Conference on Computer-Aided Design (ICCAD), pp. 556 – 562, November 1996. C05
E.S. Kuh,
J. F. Mao, and J. M. Wang, “Interconnect
simulation based on passivity and method of characteristics”, IEEE Asia and South Pacific Design Automation
Conference (ASPDAC), pp. 449 – 457, November 1996. C04 H. Wu, Z. Wei
and J. M. Wang, “A Multiple Knowledge Expression based Acquisition Tool
EDAKS”, Microcomputer, pp. 34
– 37, 1993. C03
H. Wu, Q. Zhang and J.M. Wang, “Data Exchange Interface Used on Neutral
File”, Computer Aided
Engineering, pp. 62
– 67, September 1993. C02 H. Wu, N. He and J.M. Wang, “The
Model of Inexact Reasoning of Expert System in Mechanical Design”, Computer Research and Development,
Vol. 30, pp. 51 – 57, December 1993. C01 H. Wu, Z. Wei
and J.M. Wang, “A Knowledge Acquisition Tool EDAKS Based on
Multiple-Knowledge Representation”, Computer
Research and Development, Vol. 28, pp. 30 – 32, August 1993. |
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